A little conjecture

One of my propositions in my thesis is:

February 2015 was the last month in which the world’s combined SDRAM production could have been used to cache all the traffic flowing into the Amsterdam Internet Exchange.

The underlying idea is that, if all DRAM vendors would team up (and were really committed to the idea), they could produce DRAM chips to store “The internet” at about the same rate as it is flowing into the AMS-IX. February is special, in the sense that the bandwidth of the DRAM producers is extremely close to the AMS-IX bandwidth (they are only 0.15 % apart).

DRAMeXchange reports 2402 million 2 GiB units were produced, for a total capacity of 5.16 exabits. The DRAM production bandwidth can be calculated from that number:

$$\frac{2402 \cdot 10^6 \cdot 2\cdot 2^{30} / 8~\text{bytes}}{2.419 \cdot 10^6\text{seconds in February}} = 267~GB/s$$

So far, it still holds up, as you can see here:
dram_vs_amsix_11_2015.svg

AMS-IX traffic has grown explosively over the past years, and can apparently scale up easily. It hence seems extremely likely to me that DRAM production, which is bound more physical factors, will not be able to overtake it anymore.

Source data:
ams-ix.net DRAMeXchange

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The thesis is real!

Four years and a few months of hard work condensed into 213 pages, and this is what it looks like: There are 4 more of these stacks!
128 copies (a nice round number) of my thesis `A Reconfigurable Mixed-Time-Criticality Memory Controller’ are ready to be distributed to everyone who is interested.

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My Ph.D. thesis is about real-time memory controllers, and more specifically, pattern-based memory controllers. Such controllers need to be programmed with memory patterns, which are sequences of SDRAM commands that are executed by the controller when it needs to read from or write to the memory. You can read about how these patterns are used in this article on ieeexplore. The SDRAM controller in the CompSOC platform executes these memory patterns, enabling us to give (real-time) guarantees on worst-case bandwidth and worst-case response time.

Patterns are statically computed at design time, and since this is quite a tedious process to do manually, we automated it with a publicly available tool, which you can find on the gitlab page of our group. This post describes the pypatterngen tool that creates SDRAM command schedules for DDR2/3/4 and LPDDR1/2/3 that satisfy the SDRAM timing constraints.

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This post tries to introduce the basic vhdl syntax by means of examples. Written about a year ago, its original purpose was to serve as a guide for students that started developing hardware for the CompSOC platform, but I think this info is generally useful for the world. I left most of the CompSOC specific bits in the tutorial for the sake of completion (the occasional CompSOC: label marks them). There is also a section on DTL, which may be interesting for academic readers who wonder how the sentence `DTL, which is similar to AXI‘, which I wrote in my thesis and some papers, actually holds up.

I wrote the guide with Xilinx tools in mind (version 14.7). It gradually introduces new language constructs. Although far from complete, you should be able to find most frequently used snippets in here.

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Hello World

I’ve made a new website! The change was long overdue, with the old site being not much more than a list of links with a questionable design. In this new version I’m experimenting with the hexo framework, which generates a static website based on content written in markdown. So far it seems to do what I want, but if it lets me down later, it should be easy to migrate the content.

I’ll gradually transfer content from my old site, and add new items when I come across interesting things I want to share.

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Sven Goossens

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Ph.D. Candidate at Eindhoven University of Technology